PROOFS: Sequential Circuit Fault Simulator
نویسنده
چکیده
PROOFS (Parallel RestOrative Orderindependent Fault Simulator) is a hybrid of concurrent, differential, and parallel fault simulation algorithms. It retains fault dropping advantage of concurrent method, word level parallelism of parallel method and low memory requirement of differential, while minimizing their individual disadvantages. Parallel simulation of faults reduces simulation time of PROOFS. Reduction of faults to be simulated in parallel, efficient fault injection and efficient fault ordering to reduce the number of gate evaluations are the major factors behind success of this fault simulator. Fault ordering is crucial in exploiting the benefits of parallelism. Experimental results show that fault ordering by depth first search of the circuit starting at the primary outputs achieves 40% reduction of gate evaluations over a random fault order. Unexcited fault elimination by two levels achieved 45% simulation time reduction. Results of [1] demonstrate that parallel fault simulation using 32 bit word instead of 1 bit speeds up fault simulation by six times for the largest circuit. A comparison of PROOFS with Concurrent fault simulation shows that PROOFS is 6 to 67 times faster and requires only one fifth the memory required for concurrent fault simulation on the ISCAS-89 sequential benchmark circuits. The above results obtained are based on zero delay model of gates.
منابع مشابه
IEEE International Conference on Computer - Aided Design , pp . 546 - 549 , November 1991 Methods for Reducing Events in Sequential Circuit
Methods for Reducing Events in Sequential Circuit Fault Simulation Elizabeth M. Rudnick Thomas M. Niermann Janak H. Patel Center for Reliable and Sunrise Test Systems Inc. Center for Reliable and High-Performance Computing Sunnyvale, CA 94086 High-Performance Computing University of Illinois University of Illinois Urbana, IL 61801 Urbana, IL 61801 Abstract Methods are investigated for reducing ...
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